In FinFET technologies, shorting of trench silicide to the metal gate material is becoming a yield issue due to the contact trench silicide spacing design. In addition, for long channel devices and short channel devices, workfunction chamfering also becomes problematic due to different etching rates within the differently sized spacing for these devices. In fact, long channel devices with a different gate length also shows chamfering difference.
The chamfering issue also contributes to metal gate height non-uniformity for device macros with different Lg, which causes the final metal gate height non-uniformity issue post contact recess. This problem also appears to contribute to metal gate to source/drain contact shorting issues.